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PQC: ML-KEM and ML-DSA
FIPS 203 and FIPS 204 specify the algorithms, not the silicon. That's the machines' next proving ground.
A hardware company that shouldn't be possible.
One human and a pile of machines. Production IP cores for FPGA and ASIC. Specified. Verified. Shipped.
human1
machinesmany
verification tests12,310
formal proofs41
coreAES-256-GCM
nextPQC (ML-KEM / ML-DSA)
The bet
For most of chip-design history, an IP core meant a small team: someone to write the RTL, someone to verify it, someone to own the spec. Most of the grunt work is now automatable, and that's where the machines come in. What's left is the architecture calls, the verification strategy, and the edge cases. That's the part worth doing by hand. That division of labor is the whole bet behind Synhex.
The gains compound: each core is both a product and a training ground. It leaves behind better tests, better design patterns, and a sharper sense of where the machines can be trusted. Each one moves the boundary of what one human and a pile of machines can specify, design, verify, and ship.
The longer arc
The cores are the start, not the ceiling. Teaching the machines is the long-term research program. Every core sharpens them against real hardware constraints: power, performance, and area. Every design also draws on my research and industry experience: when both hardware and AI are moving targets, the durable advantage is to keep inventing.
As the machines improve, the scope expands: single cores, then subsystems, then whole systems where they help design hardware and software together from the start. Co-designed systems are the endgame. Real silicon is the proof. Verify. Ship. Repeat.
Why cryptography first
Two reasons. First, it's where I come from: a PhD in hardware cryptography, with papers at CHES. Second, it's the part of a system where “good enough” is a vulnerability rather than a performance number. Cryptographic cores are unforgiving, which makes them a good place to prove the pipeline works. Start where the mistakes are expensive.
What ships
core
AES-256-GCM
The first proof the machines work. A family of nine AES-256-GCM cores, from area-first serial designs to a streaming core reaching a peak aggregate 1.075 Tbps post-route on Alveo U55C. Verified against NIST vectors, with formal proofs covering control, protocol, and GF(2^128) arithmetic.
Previewevaluation
A bench, not a sales call
Test the core alone or inside your own design before you license it. No NDA, no datasheet wall.
Coming soonlicense
RTL source or netlist
Integration docs come with either. Source escrow can be arranged. Betting a tape-out on one person is a reasonable thing to worry about, and I'd rather address it than dodge it.
Contact and notes
Write to me to license a core, suggest what I should build next, or share feedback on the designs, verification, and writing. You'll reach the person doing the work, not a sales rep.
I publish what comes out of this: research, new cores, explainers, and what the machines are teaching me. I'll write only when there's something worth reading. No schedule, no spam, no filler.
— Marcin Wójcik, the human